A processor-time-minimal systolic array for cubical mesh algorithms

A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms

Using a directed acyclic graph (dag) model of algorithms, the paper focuses on time-minimal multiprocessor schedules that use as few processors as possible. Such a processor-time-minimal scheduling of an algorithm’s dag first is illustrated using a triangular shaped 2D directed mesh (representing, for example, an algorithm for solving a triangular system of linear equations). Then, algorithms r...

A systolic array for pyramidal algorithms

Systolic algorithms for the CMU warp processor

CMU is building a 32-bit floating-point systolic array that can cfficicndy perform many essential computations in signal processing like the FFT and convolution. This is a one-dimensional systolic array that in general takes inputs from one end cell and produces outputs at the other end, with data and control all flowing in one direction. We call this particular systolic array the Warp processo...

Systolic Array Library for Hardware Genetic Algorithms

Genetic Algorithms (GAs) are commonly used search algorithms and there is an incentive in accelerate their execution speed using hardware. We present a collection of systolic array designs which perform the Selection, Crossover and Mutation operations of the GA. Although the premise there is considerable generality in the genetic operators is true, it is accepted that GAs often use di erent tec...

Processor-time-optimal systolic arrays

Minimizing the amount of time and number of processors needed to perform an application reduces the application's fabrication cost and operation costs. A directed acyclic graph (dag) model of algorithms is used to de ne a time-minimal schedule and a processor-time-minimal schedule. We present a technique for nding a lower bound on the number of processors needed to achieve a given schedule of a...